Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in analog domain, can further improve this advantage. An efficient multiply-accumulate cell all-analog neural layer processing macros is presented. The proposed two-quadrant multiplier circuit consists two complementary MOSFETs pulse width modulated input activation applied gates and weight signal isolated back-gate. multi-bit dynamically stored on a memory capacitor. operation result represented by charge accumulated summation line drawn from or put onto computation capacitance. Simulation results based 22 nm FD-SOI CMOS technology show that consumes about 0.67 fJ circuit-level operation. area 166 $\times$ 10 notation="LaTeX">$^{12}$ MAC/s/mm notation="LaTeX">$^2$ achieved.